1. Field of the Invention
The present invention relates to digital processing systems, and more specifically to a method and apparatus for detecting the occurrence of desired values on a bus.
2. Related Art
Buses often transfer values between components in digital processing systems (e.g., computers, machine controllers, calculators, etc.). For example, a processor sends an address of an addressable unit (e.g., memory unit or peripheral units) and receives data stored at the addressed location. Both the address and data are transmitted on a bus during such transactions. The addresses, data, and any digital values in general, are together referred to as values in the subject patent application.
A need often exists to detect the occurrence of desired values on a bus. For example, a programmer may wish to know the execution of a specific sub-routine contained in a large program, and the access of a memory location corresponding to the entry point of the sub-routine may thus be of interest. Thus, when the address of the memory location occurs on a bus storing the program instructions, the programmer can determine that the sub-routine has been accessed.
Several approaches have been used in the prior art which enable a programmer to detect the occurrence of desired values on a bus. In one approach (xe2x80x9cfirst approachxe2x80x9d), a set of comparators may be used, with each comparator comparing a bit of the value on the bus with a corresponding bit of the desired value to be detected. When all the comparators indicate match, the desired value is deemed to have occurred. One problem with such an approach is that a large number of comparators may be required when many values have to be detected. Accordingly, the approach may not scale well at least to situations when a large number of desired values are to be detected.
An alternative approach (xe2x80x9csecond approachxe2x80x9d) may address some of the deficiencies of the first approach if the values to be detected are consecutive, that is, falling within a range. In such an alternative approach, only a subset (typically the more significant bits) of the bits on the bus may be compared. The compared bit positions determine a range as is well known in the relevant arts. If a match is detected, a programmer may determine that one of the values in the range has occurred on the bus. One problem with the alternative approach is that it may be desirable to detect the occurrence of specific value (s), and the approach may not provide such information.
Another approach (xe2x80x9cthird approachxe2x80x9d) may overcome the noted problem of the second approach. The third approach may use a page-lookup random access memory (RAM) containing the same number of locations as the number of values possibly represented on a bus, but only with a single bit in each location. Each bit (memory location) of the page-lookup table may be set to one logical value to indicate that the corresponding value needs to be detected, and to another logical value otherwise.
Each value on the bus is also provided as an address to the page-lookup RAM, and the output of the page-lookup RAM indicates whether a desired value has been transmitted on the bus. Thus, using the third approach one may conveniently detect the occurrence of any desired address values (can be random). However, the approach generally requires that a page-lookup RAM have the same number of locations as the number of values possibly represented on the bus, and may not be suitable in environments using large bus width. In general, large RAMs consume a corresponding amount of space, and minimizing space consumption is desirable in many environments.
Therefore, what is needed is a method and an apparatus which potentially minimizes the additional space consumed and can yet efficiently detect the occurrence of any desired values on a bus.
A detection circuit provided in accordance with the present invention detects the occurrence of one or more desired values on a bus without requiring a large memory. In one embodiment, the detection circuit contains a monitor random access memory (RAM) and a monitor circuit. The monitor RAM contains multiple locations, with each location being addressed by a corresponding X-bit address.
Each desired value is associated with a corresponding location (in the monitor RAM) if the bits at a first set of positions matches the corresponding bits of the X-bit address (of the location). Each location contains the bits corresponding to a second set of positions of an associated desired value.
The value (xe2x80x9cpresent valuexe2x80x9d) transmitted on the bus forms the input to the detection circuit. The bits corresponding to the first set of positions of the present value are provided as an address to the monitor RAM. The monitor RAM provides the data stored at a location corresponding to the address as an output.
Monitor circuit may contain comparators which compare the output of the monitor RAM with the bits corresponding to the second set of positions of the present value to generate a result. The result indicates whether the present value equals at least one of the desired values.
Another aspect of the present invention enables multiple desired values to share the same values in the first set of positions. In one embodiment, multiple monitor RAMs are used, with different desired values sharing the same bits in the first of positions being stored at the same address in different RAMs.
Alternatively, each of the memory locations of the monitor RAM contains multiple cells, with each cell storing the bits at the second set of position of a corresponding desired value. Thus, each cell may contain a number of bits equal to the bits in the second set of positions.
The monitor circuit may contain a number of comparators equal to the number of cells in each monitor RAM location. Each comparator compares the content of the corresponding cell with the bits corresponding to the second set of positions of the present value. As a result, the output of a comparator indicates whether a desired value equals the present value received on the bus. In one embodiment, each RAM location contains four cells and accordingly four comparators may be employed.
One more aspect of the present invention enables a flag to be associated with each cell. The flag is set to one logical value (e.g., 1) if the corresponding cell stores data representing a desired value and to another logical value (0) otherwise. A valid desired value is said to be present when the flag indicates that the cell contains data representing a desired value. The comparators may generate a match only if the flag of a compared cell indicates that a desired value is represented.
According to one more aspects of the present invention, the number of bits in the first set of positions and the number of bits in the second set of positions equal the total number of bits in the desired value. In such a situation, the value in each cell (in association with the address of the location) represents a corresponding desired value. However, the bits in the first and second set of positions, need not be equal to the total number of bits in the desired value. When such an equality does not exists, the value in each cell represents a range of desired values.
In addition, the first set of positions and the second set of positions may be implemented to be in consecutive positions for simplicity of design. However, alternative embodiments can be implemented in which the positions are not consecutive. The detection circuit may be implemented in several environments such as general purpose computer systems and real time embedded systems.
Further features and advantages of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.